1. Field of the Invention
The present invention relates to a data transmitting/receiving device for transmitting and receiving data and specifically to a data transmitting/receiving device including conversion between serial data and parallel data.
2. Description of the Prior Art
Conventionally, a data transmitting/receiving device for transmitting and receiving data has been implemented in the form of a LSI device and widely utilized. Especially, a data transmitting/receiving device for transmitting and receiving serial data includes a parallel-serial conversion circuit and a serial-parallel conversion circuit because data input from/output to an internally- or externally-provided data processing section is in the form of parallel data.
FIG. 8 shows a circuit structure of a conventional data transmitting/receiving device. As shown in FIG. 8, the conventional data transmitting/receiving device 100 includes a transmission serial port 101 and reception serial port 102 for transferring a differential signal, a driver 103 for outputting transmission data TD, which is serial data, in the form of differential signal (TD+, TD−) to the transmission serial port 101, a receiver 104 for outputting differential signal (RD+, RD−) receiving at the reception serial port 102 as reception data RD which is serial data, a parallel-serial conversion circuit (P/S circuit) 105 for converting parallel data of 10-bit width to serial data, and a serial-parallel conversion circuit (S/P circuit) 106 for converting serial data to parallel data of 10-bit width. The data transmitting/receiving device 100 further includes a phase locked loop (PLL) 107 as a circuit for supplying an operation clock to the parallel-serial conversion circuit 105, and a clock recovery unit (CRU) 108 as a circuit for supplying an operation clock to the serial-parallel conversion circuit 106.
The parallel-serial conversion circuit 105 converts input data DIN [0:9], which has been supplied from an external circuit (not shown) that performs data processing, to transmission data TD of 1-bit width using internal clock CLK output from the PLL 107 as the operation clock. The transmission data TD is output to the driver 103. The PLL 107 multiplies the frequency of externally-supplied reference clock RefCLK by 10 and outputs a resultant clock as internal clock CLK.
The serial-parallel conversion circuit 106 converts reception data RD, which has been received from the reception serial port 102 through a receiver 104, to output data DOUT [0:9] of 10-bit width using recovery clock RCLK as the operation clock, and the resultant data is output to an external circuit.
In the process where reception data RD is latched and converted to parallel data in the serial-parallel conversion circuit 106, reception data RD is latched at a timing delayed by a ½ cycle from a rising edge of reception data RD, whereby bit errors are reduced and data is surely extracted.
To this end, the CRU 108 adjusts the frequency and phase of internal clock CLK to output recovery clock RCLK whose frequency is equal to that of reception data RD and whose phase is delayed by a ½ cycle with respect to that of reception data RD.
As a reliability evaluation method for the conventional data transmitting/receiving device 100, an evaluation method called a loop back test is employed wherein the transmission serial port 101 and the reception serial port 102 are connected to determined whether or not input data DIN [0:9] and output data DOUT [0:9] are identical. The loop back test is effective in checking abnormal operation of the driver 103, the receiver 104, the parallel-serial conversion circuit 105, and the serial-parallel conversion circuit 106.
In addition to the loop back test, it is preferable to measure the jitter followability (jitter tolerance) of the data transmitting/receiving device in order to evaluate whether or not the CRU 108 outputs recovery clock RCLK while following the jitter of reception data RD even if a jitter is added to reception data RD.
FIG. 9 shows a jitter tolerance measurement system for the conventional data transmitting/receiving device 100. As shown in FIG. 9, a data generator 111 generates data for test (test data) which has a 1-bit width and inputs the generated test data to the reception serial port 102 of the data transmitting/receiving device 100. Then, output data DOUT [0:9] output from the data transmitting/receiving device 100 is input to a data analyzer 112. Herein, the operation clock of the data generator 111 is modulated using a clock modulator 113 to add a predetermined jitter to the test data. Since the data analyzer 112 processes parallel data of 10-bit width, the operation clock used for the data generator 111 is divided by a frequency divider 114 into a 1/10 clock which is then supplied as the operation clock of the data analyzer 112.
However, in a jitter tolerance measurement system for the conventional data transmitting/receiving device, the data analyzer 112 obtains the operation clock through an internal PLL. Thus, even if the clock modulated by the clock modulator 113 is input to the data analyzer 112 through the frequency divider 114, modulation of the clock is filtered by a PLL provided inside the data analyzer 112. As a result, the frequency of the modulated output data DOUT output from the data transmitting/receiving device 100 is not identical to that of the operation clock of the data analyzer 112. Therefore, even when data received by the data transmitting/receiving device 100 while following the jitter of reception data RD is output with no error, it is misrecognized that a bit error has occurred. Thus, the jitter tolerance is not correctly measured.
One of the possible countermeasures against such a problem is a method wherein data in the form of serial data is supplied to the data analyzer 112 so that the jitter tolerance is measured without using the frequency divider 114 while the PLL provided inside the data analyzer is inactive.
However, in the conventional data transmitting/receiving device, if it is attempted to directly provide the serial data output from the CRU 108 to the data analyzer 112, the bit rate of received data RD is not followed because the output buffer of the data transmitting/receiving device 100 is designed so as to comply with the bit rate of output data DOUT.
As described above, in the conventional data transmitting/receiving device, parallel data is analyzed in the measurement of the jitter tolerance, and therefore, it is difficult to appropriately measure the jitter tolerance of the data transmitting/receiving device.